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a
10-Bit High Speed Multiplying D/A Converter (Universal Digital Logic Interface) DAC10*
All DAC10 series models guarantee full 10-bit monotonicity, and nonlinearities as tight as +0.05% over the entire operating temperature range are available. Device performance is essentially unchanged over the 18 V power supply range, with 85 mW power consumption attainable at lower supplies. A highly stable, unique trim method is used, which selectively shorts Zener diodes, to provide 1/2 LSB full-scale accuracy without the need for laser trimming. Single-chip reliability, coupled with low cost and outstanding flexibility, make the DAC10 device an ideal building block for A/D converters, Data Acquisition systems, CRT displays, programmable test equipment and other applications where low power consumption, input/output versatility and long-term stability are required.
FEATURES Fast Settling: 85 ns Low Full-Scale Drift: 10 ppm/ C Nonlinearity to 0.05% Max Over Temperature Range Complementary Current Outputs: 0 mA to 4 mA Wide Range Multiplying Capability: 1 MHz Bandwidth Wide Power Supply Range: +5, -7.5 Min to 18 V Max Direct Interface to TTL, CMOS, ECL, PMOS, NMOS Availability in Die Form
GENERAL DESCRIPTION
The DAC10 series of 10-bit monolithic multiplying digital-toanalog converters provide high speed performance and full-scale accuracy. Advanced circuit design achieves 85 ns settling times with very low "glitch" energy and low power consumption. Direct interface to all popular logic families with full noise immunity is provided by the high swing, adjustable threshold logic inputs.
SIMPLIFIED SCHEMATIC
MSB B1 5 LSB B10 14
V+ 15
VLC 1
B2 6
B3 7
B4 8
B5 9
B6 10
B7 11
B8 12
B9 13
BIAS NETWORK 16 CURRENT SWITCHES REFERENCE AMPLIFIER
4 2
IOUT IOUT
VREF (+)
VREF (-)
17
18 COMP
3 V-
*Protected by Patent Nos. 4,055,770, 4,056,740 and 4,092,639.
REV. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
DAC10-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter MONOTONICITY NONLINEARITY DIFFERENTIAL NONLINEARITY SETTLING TIME OUTPUT CAPACITANCE PROPAGATION DELAY OUTPUT VOLTAGE COMPLIANCE GAIN TEMPCO FULL-SCALE SYMMETRY ZERO-SCALE CURRENT FULL-SCALE CURRENT REFERENCE INPUT SLEW RATE REFERENCE BIAS CURRENT POWER SUPPLY SENSITIVITY NL DNL tS CO tPLH tPHL VOC TCIFS IFSS IZS IFR DI/dt IB PPS/FS+ PPS/FS- 4.5 V V+ -18 V -18 V V- -10 V VS = 15 V; IREF = 2 mA VS = +5 V; -7.5 V; I REF = 1 mA VS = 15 V; IREF = 2 mA VS = +5 V; -7.5 V; IREF = 1 mA VLC = 0 VLC = 0 VLC = 0; VIN = 0.8 V VIN = 2.0 V 2 -10 -5 0.001 10 (See Note) 3.960 All Bits Switched RL = 5 k RL = 0 k Full-Scale Current Change <1 LSB (See Note) IFR-IFR All Bits Switched ON or OFF Settle to 0.05% of FS (See Note) Symbol
(@ VS = 15 V; IREF = 2 mA; 0 C TA +70 C for DAC10F and G, unless otherwise noted. Output characteristics apply to both IOUT and IOUT.)
Min 10 0.3 0.3 85 18 50 50 -5.5 +10 10 0.1 0.01 3.996 6 -1 -3 25 4 0.5 4.032 3.920 0.5 1 135 DAC10F Typ Max Min 10 0.6 0.7 85 18 50 50 -5.5 +10 10 0.1 0.01 3.996 6 -1 -3 50 4 0.5 4.072 150 1 DAC10G Typ Max Units Bits LSB LSB ns pF ns ns V V ppm/C A A mA mA/s A %IFS/%V %IFS/%V mA mA mA mA mW mW V V A A
Conditions
0.001 0.01 0.0012 0.01 2.3 -9 1.8 -5.9 231 85 4 -15 4 -9 285 88 0.8 2 -10
0.001 0.01 0.0012 0.01 2.3 -9 1.8 -5.9 231 85 4 -15 4 -9 285 88 0.8 -5 0.001
POWER SUPPLY CURRENT I+ I- I+ I- POWER DISSIPATION LOGIC INPUT LEVELS LOGIC INPUT CURRENTS PD PD VIL VIH IIL IIH
10
ELECTRICAL CHARACTERISTICS
Parameter MONOTONICITY NONLINEARITY DIFFERENTIAL NONLINEARITY OUTPUT VOLTAGE COMPLIANCE FULL-SCALE CURRENT FULL-SCALE SYMMETRY ZERO-SCALE CURRENT
NOTE: Guaranteed by design.
(@ VS = 15 V; IREF = 2 mA; TA = +25 C, unless otherwise noted. Output characteristics apply to both IOUT and IOUT.)
Min 10 DAC10F Typ Max Min 10 0.3 0.3 0.5 1 -5 3.956 0.6 0.7 -6/+15 +10 3.996 0.1 0.01 1 DAC10G Typ Max Units Bits LSB LSB V
Symbol Conditions
NL DNL VOC IFS IFSS IZS Full-Scale Current Change, <1 LSB VREF = 10.000 V, R14 = R15 = 5.000 k IFR-IFR -5 3.978
-6/+18 +10 3.996 0.1 0.01 4.014 4 0.5
4.036 mA 0.4 0.5 A A
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REV. D
DAC10 WAFER TEST LIMITS
Parameter RESOLUTION MONOTONICITY NONLINEARITY OUTPUT VOLTAGE COMPLIANCE OUTPUT CURRENT RANGE ZERO-SCALE CURRENT LOGIC INPUT "1" LOGIC INPUT "0" POSITIVE SUPPLY CURRENT NEGATIVE SUPPLY CURRENT IZS VIH VIL I+ I- NL VOC True 1 LSB IFS 3.996 mA All Bits OFF IIN = 100 nA VLC @ Ground IIN = -100 A V+ = 15 V V+ = -15 V
(@ VS = 15 V, IREF = 2 mA, TA = +25 C, unless otherwise noted. Output characteristics refer to both IOUT and IOUT).
Symbol Conditions DAC10N Limit 10 10 0.5 +10 -5 18 0.5 2 0.8 4 -15 Units Bits min Bits min LSB max V max V min A max A max V min V max mA max mA max
NOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard produce dice.
TYPICAL ELECTRICAL CHARACTERISTICS refer to both I
Parameter SETTLING TIME GAIN TEMPERATURE COEFFICIENT (TC) OUTPUT CAPACITANCE OUTPUT RESISTANCE Symbol tS Conditions
(@ VS =
15 V, IREF = 2 mA, unless otherwise noted. Output characteristics OUT and IOUT).
DAC10F Typ 85 10 18 10 Units ns ppm FS/C pF M
To 1/2 LSB When Output Is Switched from 0 to FS VREF Tempco Excluded
DICE CHARACTERISTICS
DIE SIZE 0.091 0.087 inch, 7,917 sq. mils (2.311 2.210 mm, 5.107 sq. mm)
REV. D
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DAC10
ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE
Operating Temperature DAC10FX, GX, GS, GP . . . . . . . . . . . . . . . . 0C to +70C Junction Temperature (TJ) . . . . . . . . . . . . . -65C to +150C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . +300C V+ Supply to V- Supply . . . . . . . . . . . . . . . . . . . . . . . . . 36 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . V- to V- plus 36 V VLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V+ Analog Current Outputs . . . . . . . . . . . . . . . . +18 V to -18 V Reference Inputs (V16 to V17) . . . . . . . . . . . . . . . . . V- to V+ Reference Input Differential Voltage (V16 to V17) . . . . 18 V Reference Input Current (I16) . . . . . . . . . . . . . . . . . . 2.5 mA Package Type 18-Lead Hermetic DIP (X) 18-Lead SOIC (S) 18-Lead Plastic DIP (P)
JA 2 JC
Model DAC10FX DAC10GX DAC10GS DAC10GP
INL (LSB) 0.5 1 1 1
Temperature Package Package Range Description Options 0C to +70C 0C to +70C 0C to +70C 0C to +70C Cerdip Cerdip SOIC Plastic DIP Q-18 Q-18 R-18 N-18
PIN CONNECTIONS 18-Lead Hermetic DIP 18-Lead Plastic DIP
Units C/W C/W C/W
18-Lead SOIC
48 89 74
15 28 33
VLC 1 IO V-
2 3
18 17 16
COMP VREF(-) VREF(+) V+
NOTES 1 Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2 JA is specified for worst case mounting conditions, i.e., JA is specified for device in socket for Cerdip packages.
IO 4 (MSB) B1 5
DAC10
15
TOP VIEW 14 B10 (LSB) (Not to Scale) 13 B9 B2 6 B3 7 B4 8 B5 9
12 11 10
B8 B7 B6
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REV. D
Typical Performance Characteristics-DAC10
8.0 7.2
OUTPUT CURRENT - mA
TA = TMIN TO TMAX ALL BITS ON
OUTPUT VOLTAGE - Volts
+28 +24 +20 +16 +12 +8 +4 0 -4 -8
SHADED AREA INDICATES PERMISSABLE OUTPUT VOLTAGE RANGE FOR V- = -15V IREF 2.0mA FOR OTHER V- OR IREF SEE OUTPUT CURRENT vs. OUTPUT VOLTAGE CURVE
6.4 5.6 4.8 4.0 3.2 2.4 1.6 0.8 IREF = 0.2mA -6 -2 2 6 10 14 OUTPUT VOLTAGE - Volts 18 IREF = 1mA V- = -15V, V- = -10V IREF = 2mA
0mA
IOUT
1.0mA IREF = 2mA IOUT
2.0mA
(0000000000)
(11111111111)
0 -14 -10
-12
-50
0 +50 +100 +150 TEMPERATURE - C
Figure 1. True and Complementary Output Operations
Figure 2. Output Current vs. Output Voltage (Output Voltage Compliance)
Figure 3. Output Voltage Compliance vs. Temperature
10
10 POWER SUPPLY CURRENT - mA
I-
10
BITS MAY BE HIGH OR LOW I - WITH IREF = 2mA
POWER SUPPLY CURRENT - mA
POWER SUPPLY CURRENT - mA
9 8 7 6 5 4 3 2 1 0 0
9 8 7 6 5 4 3 2 1 0 0
9 8 7 6
V- = -15V IREF = 2.0mA
I-
ALL BITS "HIGH" OR "LOW"
I - WITH IREF = 1mA I - WITH IREF = 0.2mA
ALL BITS MAY BE "HIGH" OR "LOW" 5 4 3 2 1 V+ = +15V I+
I+
I - WITH IREF = 0.2mA
4 6 8 10 12 14 16 18 20 2 V+, POSITIVE POWER SUPPLY - VDC
-20 -4 -8 -12 -16 V-, NEGATIVE POWER SUPPLY - VDC
0 -50 0 +50 +100 +150 TEMPERATURE - C
Figure 4. Power Supply Current vs. V+
Figure 5. Power Supply Current vs. V-
Figure 6. Power Supply Current vs. Temperature
BASIC CONNECTIONS
+VREF
+VREF 1023 IFR = RREF 1024 2 MSB LSB
RREF IIN VIN RIN
4 IO IO
IREF 16 17 DAC10
IO + IO = IFR FOR ALL LOGIC STATES RREF (R16) IREF R17 17
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 5 6 7 8 9 10 11 12 13 14
+VREF
16 DAC10 3 CC COMP 0.1 F V- 0.01 F V+ VLC 18 15 1
2
IREF RREF RREF VIN R17 +VREF R17
(OPTIONAL)
PEAK NEGATIVE SWING OF IIN
FOR FIXED REFERENCE, TTL OPERATION, TYPICAL VALUES ARE: VREF = +10.000V RREF = 5.000k R15 = RREF CC = 0.01 F VLC = 0V (GROUND)
16 DAC10 17
HIGH INPUT IMPEDANCE +VREF MUST BE ABOVE PEAK POSITIVE SWING OF VIN
Figure 7. Basic Positive Reference Operation
Figure 8. Accommodating Bipolar References
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection.
WARNING!
ESD SENSITIVE DEVICE
REV. D
-5-
DAC10
RREF
VREF +10V LOW T.C. 4.5k 16 39k IREF(+) 2mA 10k POT 1V 17
16 DAC10
4 2
IO IO
DAC10
-VREF -VREF RREF
R17
17
IFS
2
NOTE: RREF SETS IFS; R17 IS FOR BIAS CURRENT CANCELLATION
APPROXIMATELY 5k
Figure 9. Basic Negative Reference Operation
Figure 10. Recommended Full-Scale Adjustment Circuit
MSB
LSB FULL RANGE EO HALF-SCALE +LSB HALF-SCALE HALF-SCALE -LSB HALF-SCALE +LSB ZERO SCALE +LSB EO
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 1 1 1 0 0 0 111 000 000 111 000 000 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0
IOmA 3.996 2.004 2.000 1.996 0.004 0.000
IOmA 0.000 1.992 1.996 2.000 3.992 3.996
EO -4.995 -2.505 -2.500 -2.495 -0.005 0.000
EO -0.000 -2.490 -2.495 -2.500 -4.990 -4.995
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 4 1.25k 1.25k IO 2
IREF = 2.000mA
16
IO DAC10
Figure 11. Basic Unipolar Negative Operation
MSB
LSB
+5V POSITIVE FULL RANGE POSITIVE FULL RANGE -LSB 2.5k 4 EO 2.5k ZERO-SCALE +LSB ZERO-SCALE ZERO-SCALE -LSB NEGATIVE FULL-SCALE +LSB NEGATIVE FULL-SCALE
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 1 1 1 1 1 0 0 111 111 000 000 111 000 000 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 11 10 01 00 11 01 00
EO -4.990 -4.980 -0.010 0.000 +0.010 +4.990 +5.000
EO +5.000 +4.990 +0.020 +0.010 0.000 -4.980 -4.990
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
IREF (+) = 16 2.000mA
IO DAC10 IO
2
EO
Figure 12. Basic Bipolar Output Operation
5k +15V 2 VIN VO REF01 GND 4 V+ V- 6 5.000 k 5k DAC10 CC VLC IO 2 -15V MSB LSB B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 2.5k +15V IO 4 POSITIVE FULL RANGE EO ZERO-SCALE NEGATIVE FULL-SCALE B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 1 1 111 000 000 000 1 0 0 0 11 00 00 00 1 0 0 0 11 00 01 00 EO +4.990 0.00 -4.990 -5.000
NEGATIVE FULL-SCALE +LSB 0 0
Figure 13. Offset Binary Operation
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REV. D
DAC10
LOW-TO-HIGH SETTLING VL = 16.500V 0.001V HIGH-TO-LOW SETTLING VL = 0.500V 0.001V VL
51
0.500V
0.001V
+15V
0.1 F
4k
10 F 0.1 F IN5711 10 F 0.01 F 4.7 F
5 D.U.T. 15 16 18 0.01 F 3 17 1
14 4 2 2N918
2N918 VO
2k
175mV
1F -15V
1k
+15V
1F
1M 1/4W, 5% CARBON
499k 1/4W, 5% CARBON
-15V 0.01 F 1/2 LSB SETTLING = 7.8mV
2.5k
-15V 4.7 F
+15V 2 REF-01 4
2.5k
0.01 F -15V
6 5
10k
NOTES: 1. CASE OF 2N918s MUST BE GROUNDED. 2. RESISTORS ARE 1/4W MF, 1% UNLESS OTHERWISE SPECIFIED. 3. USE FET PROBE (7A11 SCOPE PLUGIN).
Figure 14. Settling Time Measurement
RL
TTL VTH = +1.4V
+15V VTH = VLC +1.4V +15V CMOS VTH = +7.6V VLC 6.2k 0.1 F
4 DAC10 2
IO IO OP01 EO 0 TO +IFR RL
DAC10 VLC 1
9.1k
IFR = 1023 2 IREF 1024 FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC), CONNECT INVERTING INPUT OF OP AMP TO IO (PIN 2); CONNECT IO (PIN 4) TO GROUND.
ECL
Figure 15. Positive Low Impedance Output Operation
13k 2N3904 2N3904 3k
4 DAC10 2 IO IO RL OP15 0 TO -IFR IFR = 1023 1024 EO
"A"
39k
RL 2 IREF
TO PIN 1 VLC 6.2k
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC), CONNECT NOINVERTING INPUT OF OP AMP TO IO PIN 2); CONNECT IO (PIN 4) TO GROUND.
-5.2V
Figure 16. Negative Low Impedance Output Operation
Figure 17. Interfacing with Various Logic Families
REV. D
-7-
DAC10
APPLICATIONS
+VREF RREF RIN 0V OPTIONAL RESISTOR FOR OFFSET INPUTS 16 REQ = 800 RP TYPICAL VALUES: RIN = 1k +VIN = 2V 1 REQ = 1 + 1 + 1 RIN RP RREF 17 2 DAC10 4 RL RL
Multiplying Operation
The DAC10 provides excellent multiplying performance with an extremely linear relationship between IFS and IREF over a range of 4 mA to 4 A. Monotonic operation is maintained over a typical range of IREF from 100 A to 2 mA.
Reference Amplifier Compensation for Multiplying Applications
NO CAP
AC reference applications will require the reference amplifier to be compensated using a capacitor from Pin 18 to V-. The value of this capacitor depends on the impedance presented to Pin 16 for R16 values of 1.0 k, 2.5 k and 5.0 k, minimum values of CC are 15 pF, 37 pF and 75 pF. Larger values of R16 require proportionately increased values of CC for proper phase margin. For fastest response to a pulse, low values of R16 enabling small CC values should be used. If Pin 16 is driven by a high impedance such as a transistor current source, none of the above values will suffice and the amplifier must be heavily compensated, which will decrease overall bandwidth and slew rate. For R16 = 1 k and CC = 15 pF, the reference amplifier slews at 4 mA/s enabling a transition from IREF = 0 to IREF = 2 mA in 500 ns. Operation with pulse inputs to the reference amplifier may be accommodated by an alternate compensation scheme. This technique provides lowest full-scale transition times. An internal clamp allows quick recovery of the reference amplifier from a cutoff (IREF = 0) condition. Full-scale transition (0 mA to 2 mA) occurs in 120 ns when the equivalent impedance at Pin 16 is 200 and CC = 0. This yields a reference slew rate of 16 mA/ s, which is relatively independent of RIN and VIN values.
LOGIC INPUTS
Figure 18. Pulsed Reference Operation
Reference Amplifier Setup
The DAC10 is a multiplying D/A converter in which the output current is the product of a digital number and the input reference current. The reference current may be fixed or may vary from nearly zero to 2 mA. The full-scale output current is a linear function of the reference current and is given by:
I FR = 1023 x 2 x I REF 1024
where IREF equals current flowing into Pin 16. In positive reference applications, an external positive reference voltage forces current through R16 into the VREF (+) terminal (Pin 16) of the reference amplifier. Alternatively, a negative reference may be applied to VREF (-) at Pin 17; reference current flows from ground through R16 into V(+) as in the positive reference case. This negative reference connection has the advantage of a very high impedance presented at Pin 17. R17 (nominally equal to R16) is used to cancel bias current errors; R17 may be eliminated with only a minor increase in error. Bipolar references may be accommodated by offsetting VREF or Pin 17. The negative common-mode range of the reference amplifier is given by: VCM- = V- plus (IREF x 2 k) plus 2 V. The positive common-mode range is V+ less 1.8 V. When a dc reference is used, a reference bypass capacitor is recommended. A 5 V TTL logic supply is not recommended as a reference. If a regulated power supply is used as a reference, R16 should be split into two resistors with the junction bypassed to ground with a 0.1 F capacitor. For most applications, the tight relationship between IREF and IFS will eliminate the need for trimming IREF. If required, fullscale trimming may be accomplished by adjusting the value of R16, or by using a potentiometer for R16. An improved method of full-scale trimming that eliminates potentiometer TC effect is shown in the Recommended Full-Scale Adjustment circuit. The reference amplifier must be compensated by using a capacitor from Pin 18 to V-. For fixed reference operation, a 0.01 F capacitor is recommended. For variable reference applications, see section entitled Reference Amplifier Compensation for Multiplying Applications.
The DAC10 design incorporates a unique logic input circuit that enables direct interface to all popular logic families and provides maximum noise immunity. This feature is made possible by the large input swing capability, 2 A logic input current and completely adjustable logic threshold voltage. For V- = -15 V, the logic inputs may swing between -5 and +18 V. This enables direct interface with +15 V CMOS logic, even when the DAC10 is powered from a +5 V supply. Minimum input logic swing and minimum logic threshold voltage are given by: V- plus (lREF x 2 k) plus 3 V. The logic threshold may be adjusted over a wide range by placing an appropriate voltage at the logic threshold control Pin (Pin 1, VLC). The appropriate graph shows the relationship between VLC and VTH over the temperature range, with VTH nominally 1.4 V above VLC. For TTL interface, simply ground Pin 1. When interfacing ECL, an IREF = 1 mA is recommended. For interfacing other logic families, see Figure 17. For general setup of the logic control circuit, it should be noted that Pin 1 will sink 1.1 mA typical; external circuitry should be designed to accommodate this current. Fastest settling times are obtained when Pin 1 sees a low impedance. If Pin 1 is connected to a 1 k divider, for example, it should be bypassed to ground by a 0.01 F capacitor.
-8-
REV. D
DAC10
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided where IO + IO = I FS . Current appears at the "true" output when a "1" is applied to each logic input. As the binary count increases, the sink current at Pin 4 increases proportionally, in the fashion of a "positive logic" D/A converter. When a "0" is applied to any input bit, that current is turned off at Pin 4 and turned on at Pin 2. A decreasing logic count increases IO as in a negative or inverted logic D/A converter. Both outputs may be used simultaneously. If one of the outputs is not required, it must still be connected to ground or to a point capable of sourcing IFS. DO NOT LEAVE AN UNUSED OUTPUT PIN OPEN. Both outputs have an extremely wide voltage compliance enabling fast direct current-to-voltage conversion through a resistor tied to ground or other voltage source. Positive compliance is 36 V above V- and is independent of the positive supply. Negative compliance is +10 V above V-. The dual outputs enable double the usual peak-to-peak load swing when driving loads in quasi-differential fashion. This feature is especially useful in cable driving, CRT deflection and in other balanced applications such as driving center-tapped coils and transformers.
POWER SUPPLIES
The temperature coefficient of the reference resistor, R14, should match and track that of the output resistor for minimum overall full-scale drift. Settling times of the DAC10 decrease approximately 10% at -55C; an increase of about 15% is typical at +125C.
SETTLING TIME
The DAC10 is capable of extremely fast settling times; typically 85 ns at IREF = 2 mA. Judicious circuit design and careful board layout must be employed to obtain full performance potential during testing and application. The logic switch design enables propagation delays of only 35 ns for each of the 10 bits. Settling time to within 1/2 LSB of the LSB is therefore 35 ns, with each progressively larger bit taking successively longer. The MSB settles in 85 ns, thus determining the overall settling time of 130 ns. Settling to 8-bit accuracy requires about 60 ns to 78 ns. The output capacitance of the DAC10, including the package, is approximately 18 pF; therefore, the output RC time constant dominates settling time if RL > 500 . Settling time and propagation delay are relatively insensitive to logic input amplitude and rise and fall times, due to the high gain of the logic switches. Settling time also remains essentially constant for IREF values down to 1 mA, with gradual increases for lower IREF values. The principal advantage of higher IREF values lies in the ability to attain a given output level with lower load resistors, thus reducing the output RC time constant. Measurement of settling time requires the ability to accurately resolve 2 A; therefore, a 4 k load is needed to provide adequate drive for most oscilloscopes. The settling time fixture of schematic titled "Settling Time Measurement" uses a cascode design to permit driving a 4 k load with less than 5 pF of parasitic capacitance at the measurement node. At IREF values of less than 1 mA, excessive RC damping of the output is difficult to prevent while maintaining adequate sensitivity. However, the major carry from 0111111111 to 1000000000 provides an accurate indicator of settling time. This code change does not require the normal 6.2 time constants to settle to within 0.2% of the final value, and thus settling times may be observed at lower values of IREF. DAC10 switching transients or "glitches" are very low and may be further reduced by small capacitive loads at the output with a minor sacrifice in settling time. Fastest operation can be obtained by using short leads, minimizing output capacitance and load resistor values, and by adequate bypassing at the supply, reference and VLC terminals. Supplies do not require large electrolytic bypass capacitors as the supply current drain is independent of input logic states; 0.1 F capacitors at the supply pins provide full transient protection.
The DAC10 operates over a wide range of power supply voltages from a total supply of 9 V to 36 V. When operating with V- supplies of -10 V or less, IREF 1 mA is recommended. Low reference current operation decreases power consumption and increases negative compliance, reference amplifier negative common-mode range, negative logic input range and negative logic threshold range; consult the various figures for guidance. For example, operation at -9 V with IREF = 2 mA is not recommended because negative output compliance would be reduced to near zero. Operation from lower supplies is possible, however at least 8 V total must be applied to ensure turn-on of the internal bias network. Symmetrical supplies are not required, as the DAC10 is quite insensitive to variations in supply voltage. Battery operation is feasible as no ground connection is required; however, an artificial ground may be used to ensure that logic swings, etc., remain within acceptable limits.
TEMPERATURE PERFORMANCE
The nonlinearity and monotonicity specifications of the DAC10 are guaranteed to apply over the entire rated operating temperature range. Full-scale output current drift is tight, typically +10 ppm/C, with zero-scale output current and drift essentially negligible compared to 1/2 LSB.
REV. D
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DAC10
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
18-Lead Cerdip (Q-18)
0.005 (0.13) MIN
18
0.098 (2.49) MAX
10
0.310 (7.87) 0.220 (5.59)
1 9
PIN 1 0.960 (24.38) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 0.100 (2.54) BSC 0.070 (1.78) SEATING 0.030 (0.76) PLANE
0.320 (8.13) 0.290 (7.37)
15 0
0.015 (0.38) 0.008 (0.20)
18-Lead Plastic DIP (N-18)
0.925 (23.49) 0.845 (21.47)
18 1 10 9
0.280 (7.11) 0.240 (6.10)
PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15)
0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN SEATING PLANE
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.015 (0.381) 0.008 (0.204)
18-Lead Wide Body SOL (R-18)
0.4625 (11.75) 0.4469 (11.35)
18 10
0.2992 (7.60) 0.2914 (7.40)
1 9
0.4193 (10.65) 0.3937 (10.00)
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) x 45 0.0098 (0.25)
0.0118 (0.30) 0.0040 (0.10)
8 0.0500 (1.27) 0.0500 0.0192 (0.49) 0 0.0157 (0.40) (1.27) 0.0138 (0.35) SEATING 0.0125 (0.32) PLANE BSC 0.0091 (0.23)
-10-
REV. D
PRINTED IN U.S.A.
C3134-0-5/98

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